HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 573

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit 5—Timer Enable (TME): Enables or disables the timer.
Bits 4 and 3—Reserved: These bits are always read as 1. The write value should always be 1.
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources for input to WTCNT. The clock signals are obtained by dividing the frequency of the
system clock ( ).
Note: * The overflow interval listed is the time from when the WTCNT begins counting at H'00 until
13.2.3
Note: * Only 0 can be written in bit 7, to clear the flag.
RSTCSR is an 8-bit read/write register that controls output of the reset signal generated by
watchdog timer counter (WTCNT) overflow and selects the internal reset signal type. The method
Bit 5: TME
0
1
Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Source
0
1
Initial value:
an overflow occurs.
Reset Control/Status Register (RSTCSR)
R/W:
0
1
0
1
Bit:
R/(W) *
WOVF
7
0
Description
Timer disabled: WTCNT is initialized to H'00 and count-up stops
Timer enabled: WTCNT starts counting. A WDTOVF signal or interrupt
is generated when WTCNT overflows
0
1
0
1
0
1
0
1
RSTE
R/W
6
0
RSTS
/4 (Initial value)
/128
/256
/512
/1024
/2048
/8192
/16384
R/W
5
0
—
R
4
1
Rev. 2.00 Mar 09, 2006 page 547 of 906
Overflow Interval * ( = 60 MHz)
17.0 µs
544 µs
1.1 ms
2.2 ms
4.4 ms
8.7 ms
34.8 ms
69.6 ms
Section 13 Watchdog Timer (WDT)
—
Description
R
3
1
—
R
2
1
REJ09B0292-0200
—
R
1
0
(Initial value)
—
R
0
1