HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 135

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Double data transfer instructions (MOVX.W, MOVY.W, MOVX.L, and MOVY.L):
Instruction formats of double data transfer instructions are shown in table 3.12. With double data
transfer group instructions, X memory and Y memory can be accessed in parallel.
In this case, the specific buses called X bus and Y bus are used to access X memory and Y
memory, respectively. To fetch the CPU instructions, the L bus is used. Accordingly, no conflict
occurs among X, Y, and L buses.
Load instructions for X memory specify the X0 or X1 register as the destination operand. Load
instructions for Y memory specify the Y0 or Y1 register as the destination operand. Store
registers for X or Y memory specify the A0 or A1 register as the source operand. The double data
transfer instructions use only word data (16 bits). When a word data transfer instruction is
executed, the upper word of register operand is used. To load word data, data is loaded to the
upper word of the destination register and the lower word of the destination register is
automatically cleared to 0.
Double data transfer instructions can be described in parallel to the DSP operation instructions.
Even if a conditional operation instruction is specified in parallel to a double data transfer
Legend
XAB
XDB
YAB
YDB
LAB
LDB
CDB
: X bus (address)
: X bus (data)
: Y bus (address)
: Y bus (data)
: L bus (address)
: L bus (data)
: C bus (data)
X memory
Y memory
XAB
[15:0]
Figure 3.4 DSP Registers and Bus Connections
YAB
[15:0]
XDB
[15:0]
YDB
[15:0]
CPU
DSP unit
CDB
[31:0]
Rev. 1.00, 02/04, page 97 of 804
DSR
A0
A1
M0
M1
X0
X1
Y0
Y1
A0G
A1G
LAB
[31:0]
LDB
[31:0]