HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 615

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
4
3
2
1
0
Bit name
RWUPS
RSME
PWMD
ASCE
SOFME
Initial
value
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
Description
Remote Wakeup Status
Status bit to indicate that the remote wakeup from the
host is enabled/disabled. Indicates 0 when the remote
wakeup is disabled with Device Remote Wakeup by the
Set Feature/Clear Feature request and indicates 1 when
it is enabled.
Resume Enable
Bit to clear the suspend state (performs the remote
wakeup)
When this bit is written to 1, a resume register is set.
When this bit will be used, be sure to hold to 1 for one
clock or more at 12 MHz in minimum and then clear to 0
again.
Power Mode Select
0: USBF is operated in self-powered mode
1: USBF is operated in bus-powered mode
Automatic Stall Clear Enable
When this bit is set to 1, the stall handshake is returned
to the host and the stall setting bit (EPSTLR/EPxSTL) of
the returned endpoint is automatically cleared. Control in
a unit of endpoint is disabled as this bit is common for all
endpoints. When this bit is set to 0, be sure to clear the
stall setting bit of each endpoint by using software.
Enable this bit before setting EPSTL to 1.
SOF Marker Function Enable
Controls SOF marker function.
When this bit is set to 1, the SOF interrupt flag is set to 1
every 1 msec even if an SOF packet is broken. Before
setting this bit to 1, check if the SOF interrupt flag of
IFR0 register is detected correctly. If a suspension is
detected, this bit must be cleared to 0. Before setting
this bit to 1 again, check the SOF detection.
Rev. 1.00, 02/04, page 577 of 804