HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 145

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

3.5
3.5.1
There are eight data registers (A0, A1, X0, X1, Y0, Y1, M0 and M1) and one control register
(DSR) as DSP registers (figure 3.3).
Four kinds of operation access the DSP data registers. The first is DSP data processing. When a
DSP fixed-point arithmetic operation instruction uses A0 or A1 as the source register, it uses the
guard bits (bits 39 to 32). When it uses A0 or A1 as the destination register, guard bits 39 to 32 are
valid. When a DSP fixed-point arithmetic operation instruction uses a DSP register other than A0
or A1 as the source register, it sign-extends the source register value to bits 39 to 32. When it uses
one of these registers as the destination register, bits 39 to 32 of the result are discarded.
The second kind of operation is an X or Y data transfer operation, MOVX.W, MOVY.W. This
operation accesses the X and Y memories through the 16-bit X and Y data buses (figure 3.4). The
register to be loaded or stored by this operation always comprises the upper 16 bits (bits 31 to 16).
X0 or X1 can be the destination register of an X memory load and Y0 or Y1 can be the destination
of a Y memory load, but no other register can be the destination register in this operation. When
data is read into the upper 16 bits of a register (bits 31 to 16), the lower 16 bits of the register (bits
15 to 0) are automatically cleared. A0 and A1 can be stored in the X or Y memory by this
operation, but no other registers can be stored.
The third kind of operation is a single-data transfer instruction, MOVS.W or MOVS.L. These
instructions access any memory location through the LDB (figure 3.4). All DSP registers connect
to the LDB and can be the source or destination register of the data transfer. These instructions
have word and longword access modes. In word mode, registers to be loaded or stored by this
instruction comprise the upper 16 bits (bits 31 to 16) for DSP registers except A0G and A1G.
When data is loaded into a register other than A0G and A1G in word mode, the lower half of the
register is cleared. When A0 or A1 is used, the data is sign-extended to bits 39–32 and the lower
half is cleared. When A0G or A1G is the destination register in word mode, data is loaded into an
8-bit register, but A0 or A1 is not cleared. In longword mode, when the destination register is A0
or A1, it is sign-extended to bits 39 to 32.
The fourth kind of operation is system control instructions such as LDS, STS, LDS.L, or STS.L.
The DSR, A0, X0, X1, Y0, and Y1 registers of the DSP register can be treated as system registers.
For these registers, data transfer instructions between the CPU general registers and system
registers or memory access instructions are supported.
Tables 3.14 and 3.15 show the data type of registers used in DSP instructions. Some instructions
cannot use some registers shown in the tables because of instruction code limitations. For
example, PMULS can use A1 as the source register, but cannot use A0. These tables ignore details
of register selectability.
DSP Data Operation Instructions
DSP Registers
Rev. 1.00, 02/04, page 107 of 804