HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 40
HD6417660
Manufacturer Part Number
HD6417660
Description
Renesas 32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417660.pdf
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Table 1.1
Rev. 1.00, 02/04, page 2 of 804
Item
CPU
DSP unit
SH7660 Features
Features
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Renesas Technology Original SuperH architecture
Compatible with SH-1, SH-2 and SH-3 at object code level
32-bit internal data bus
Supports various registers
Sixteen 32-bit general registers (including eight 32-bit bank registers)
Five 32-bit control registers
Four 32-bit system registers
Supports RISC-type instruction set
Instruction length: 16-bit fixed length for improved code efficiency
Load/store architecture
Delayed branch instructions
Instruction set suitable for C language
Supports barrel shift instructions and multiply-and-accumulate instructions
Instruction execution time: One instruction/cycle for basic instructions
Logical address space: 4 Gbytes
Five-stage pipeline
Mixture of 16-bit and 32-bit instructions
32-/40-bit internal data bus
Employs multiplier, ALU, and barrel shifter
16-bit × 16-bit → 32-bit one cycle multiplier
Employs large-capacity DSP data register files
Six 32-bit data registers
Two 40-bit data registers
Extended harvard architecture for DSP data bus
Two data buses
One instruction bus
Maximum four parallel operations: ALU, multiply, and two load or store
Two addressing units to generate addresses for two memory access
DSP data addressing modes: Increment and indexing (with or without
modulo addressing)
Zero-overhead repeat loop control
Conditional execution instructions
User DSP mode and privileged DSP mode
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