HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 473
HD6417660
Manufacturer Part Number
HD6417660
Description
Renesas 32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417660.pdf
(846 pages)
- Current page: 473 of 846
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This LSI has a two-channel serial communication interface with on-chip FIFO buffers (Serial
Communication Interface with FIFO: SCIF). The SCIF can perform asynchronous and clock
synchronous serial communication.
64-stage FIFO registers are provided for both transmission and reception, enabling fast, efficient,
and continuous communication.
16.1
• Asynchronous mode
• Clock synchronous mode
• Full-duplex communication capability
• On-chip baud rate generator allows any bit rate to be selected.
• Choice of serial clock source: internal clock from baud rate generator or external clock from
SCIS3C2B_010020030200
Serial data communication is executed using an asynchronous system in which
synchronization is achieved character by character. Serial data communication can be carried
out with standard asynchronous communication chips such as a Universal Asynchronous
Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
There is a choice of eight serial data communication formats.
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: Even/odd/none
LSB-first transfer
Receive error detection: Parity, framing, and overrun errors
Break detection: If a framing error is followed by at least one frame at the space “0” (low)
Serial data communication is synchronized with a clock. Serial data communication can be
carried out with other chips that have a synchronous communication function.
Data length: 8 bits
LSB-first transfer
The transmitter and receiver are independent units, enabling transmission and reception to be
performed simultaneously.
The transmitter and receiver both have a 64-stage FIFO buffer structure, enabling fast and
continuous serial data transmission and reception.
SCK pin.
Section 16 Serial Communication Interface with FIFO
level, a break is detected.
Features
(SCIF)
Rev. 1.00, 02/04, page 435 of 804
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