HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 514

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

16.4.5
Serial Operation in Clock Synchronous Mode
One unit of transfer data (character or frame)
*
*
Serial clock
LSB
MSB
Serial data
don't care
don't care
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Note: * High except in continuous transmission/reception
Figure 16.12 Data Format in Clock Synchronous Communication
In clock synchronous serial communication, data on the communication line is output from a
falling edge of the serial clock to the next falling edge. Data is guaranteed valid at the rising edge
of the serial clock.
In serial communication, each character is output starting with the LSB and ending with the MSB.
After the MSB is output, the communication line remains in the state of the MSB.
In clock synchronous mode, the SCIF receives data in synchronization with the rising edge of the
serial clock.
Data Transfer Format: A fixed 8-bit data format is used. No parity or multiprocessor bits are
added.
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
through the SCK pin can be selected as the serial clock for the SCIF, according to the setting of
the CKE1 and CKE0 bits in SCSCR.
Eight serial clock pulses are output in the transfer of one character, and when no
transmission/reception is performed, the clock is fixed high. However, when the operation mode is
reception only, the synchronous clock output continues while the RE bit is set to 1. To fix the
clock high every time one character is transferred, write to the transmit FIFO data register
(SCFTDR) the same number of dummy data bytes as the data bytes to be received and set the TE
and RE bits to 1 at the same time to transmit the dummy data. When the specified number of data
bytes are transmitted, the clock is fixed high.
Rev. 1.00, 02/04, page 476 of 804