HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 701
HD6417660
Manufacturer Part Number
HD6417660
Description
Renesas 32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417660.pdf
(846 pages)
- Current page: 701 of 846
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25.2.8
Break bus cycle register B (BBRB) is a 16-bit readable/writable register, which specifies (1) X bus
or Y bus, (2) L bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and
(5) operand size in the break conditions of channel B.
Bit
15 to 10
9
8
7
6
5
4
Break Bus Cycle Register B (BBRB)
Bit Name
XYE
XYS
CDB1
CDB0
IDB1
IDB0
Initial
Value R/W
All 0
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0. If 1 is written to these bits, correct operation
cannot be guaranteed.
Selects the X memory bus or Y memory bus as the
channel B break condition. Note that this bit setting is
enabled only when the L bus is selected with the CDB1
and CDB0 bits. Selection between the X memory bus and
Y memory bus is done by the XYS bit.
0: Selects L bus for the channel B break condition
1: Selects X/Y memory bus for the channel B break
Selects the X bus or the Y bus as the bus of the channel B
break condition.
0: Selects the X bus for the channel B break condition
1: Selects the Y bus for the channel B break condition
L Bus Cycle/I Bus Cycle Select B
Select the L bus cycle or I bus cycle as the bus cycle of the
channel B break condition.
00: Condition comparison is not performed
01: The break condition is the L bus cycle
10: The break condition is the I bus cycle
11: The break condition is the L bus cycle
Instruction Fetch/Data Access Select B
Select the instruction fetch cycle or data access cycle as
the bus cycle of the channel B break condition.
00: Condition comparison is not performed
01: The break condition is the instruction fetch cycle
10: The break condition is the data access cycle
11: The break condition is the instruction fetch cycle or
unconditionally
condition
data access cycle
Rev. 1.00, 02/04, page 663 of 804
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