PSB7238 SIEMENS [Siemens Semiconductor Group], PSB7238 Datasheet - Page 37

• Manufacturer Part Number: PSB7238
• Description: Joint Audio Decoder-Encoder - Multimode
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Table 11
For reading a register from
address
(2000
For writing a register at
address
(2000
status to be generated on INT1 to the DSP, and the Interrupt Host Busy bit INHB
(address 50
status, the DSP (firmware) reads address 3050
automatically resets the HINT interrupt status bit in the DSP Interrupt Status Register for
INT1 (address 3074
that it is ready to accept a new interrupt from the host, which it would usually (but not
necessarily) do after it has read the INH register. The 16-bit control register located at
60/61
interrupt. Please refer to the specific interface procedures for details.
Software Interrupts
For communication between the host software and the DSP software, the soft interrupt
registers IND (from DSP to host) and INH (from host to DSP) can be used.
Interrupt from Host to DSP
A write operation by the host to address 50
Semiconductor Group
H
H
H
(3060/3061
+ a5:0)
+ a5:0)
H
, readable by host) to be set to ‘1’. Having recognized an INH interrupt
H
) may contain additional information for the DSP to read after an INH
H
). The INHB bit can be written by the DSP again to ‘0’ to indicate
Host writes byte: 1 0 a5 a4 a3 a2 a1 a0 to address 40
This causes RDY bit to be set to 0. Internally, an RACC
interrupt status (INT1 line) is generated to the DSP.
Firmware:
DSP reads address 3040
(most significant bit = 1), fetches data from (2000
writes into 3041
‘1’.
After polling RDY bit to be ‘1’, the host can read the data
from 41
Host writes data into address 41
Host writes byte: 0 0 a5 a4 a3 a2 a1 a0 to address 40
This causes RDY bit to be set to 0. Internally, an RACC
interrupt status (INT1 line) is generated to the DSP.
Firmware:
DSP reads address 3040
(most significant bit = 0), fetches data from 3041
into (2000
to ‘1’.
After polling RDY bit to be ‘1’, the host can access 40
another operation.
H
, and access 40
H
+ a5:0), and sets RDY bit (address 3040
37
H
H
and sets RDY bit (address 3040
(INH) causes a maskable INH interrupt
Interfaces and Memory Organization
H
H
H
H
, recognizes a “read” access
for another operation.
, recognizes a “write” access
(INH). This read operation
H
.
Data Sheet 1998-07-01
PSB 7238
H
H
, writes it
H
+ a5:0),
/40
H
/40
H
H
H
H
) to
.
.
for
H
)