PSB7238 SIEMENS [Siemens Semiconductor Group], PSB7238 Datasheet - Page 46

• Manufacturer Part Number: PSB7238
• Description: Joint Audio Decoder-Encoder - Multimode
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
Note: When the PSB 7238 is reset via the RESET input, the following consecutive
Note: After a hardware reset, the JADE firmware needs to initialize its internal memories
Power-Down
The actual chip internal clock (“DSP clock”) is gated with the PU bit in the general
configuration/control register. Thus, when PU is set to ‘0’ (either via the host or the DSP),
clock distribution is stopped and the DSP is disabled. In this mode the power
consumption is minimum (software power-down). Only an interrupt to the DSP (on INT0
or INT1) can restart the DSP clock.
The initial state of the PU bit is ‘1’.
The PU bit is used by the on-chip firmware for the firmware-controlled power-down (see
Chapter 6.1.3 for details).
IOM
The IOM-2 clocking is either provided by separate timing inputs DCL and FSC,
independent of the other clocks, or may be generated by the JADE itself (CGEN bit in
register 202B
(DCL = 1.536 MHz, FSC = 8 kHz) is supported.
When input, the DCL clock frequency is either equal to the data rate on DD/DU (if Clock
Rate Select bit CRS = 1) or twice the bit rate (if CRS = 0, default value after reset). In the
last case it is ensured that the internal IOM-2 bit clock has a phase such that output bits
on DD/DU are correctly clocked out (see Figure 17).
– the PLL is initialized depending on the pin CM1
– if the PLL is chosen as a clock source, the PLL (frequency multiplier) goes through
– after the clock has become stable, the PSB 7238 (including the DSP) requires
– As a consequence, for a proper initialization the required total length of the RESET
®
a transient state where the clock is not yet stable
42 clock cycles to be fully initialized.
is 1 ms.
-2 Clocks
actions take place internally:
and interfaces. The time to do this is less than 10 ms. The user must take care to
access the JADE only after this initialization phase is completed, i.e. 10 ms after
the hardware reset.
H
). When generated by the JADE, only double rate clocking in TE mode
46
Data Sheet 1998-07-01
Functional Blocks
PSB 7238