PSB7238 SIEMENS [Siemens Semiconductor Group], PSB7238 Datasheet - Page 84

• Manufacturer Part Number: PSB7238
• Description: Joint Audio Decoder-Encoder - Multimode
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
Acknowledge Register
77
76
The interrupt status bit is reset when the host writes a ‘1’ in the corresponding bit
position. The other interrupts are acknowledged as follows:
DINT
HDLC1
HDLC2
MDR
GPI
CIC1
CIC2
Note: Since no direct access to the MONR, CIR1, CIR2 and GP Int Status registers for
H
H
the host is allowed (these registers are in the configuration and control register
area 2000
registers as decribed in Section 2 – in principle giving the host the possibility to
handle the Monitor and C/I channels via the DSP.
Reset when IND Int. Status register is read
Reset when HDLC Controller 1 interrupt register is read
Reset when HDLC Controller 2 interrupt register is read
Reset when MONR register is read
Reset when GP Int Status register is read
Reset when CIR1 register is read
Reset when CIR2 register is read.
Bit 15
Bit 7
T1
H
upwards), they are read using the procedure via address and data
MER
T2
MDA
T3
SAIN
MEA
84
MAB
Register Description
Data Sheet 1998-07-01
PSB 7238
Bit 8
Bit 0