ICE2QR0665_10 INFINEON [Infineon Technologies AG], ICE2QR0665_10 Datasheet - Page 9

• Manufacturer Part Number: ICE2QR0665_10
• Description: Off-Line SMPS Quasi-Resonant PWM Controller
• Manufacturer: INFINEON [Infineon Technologies AG]

thedetected zero-crossing to the switch-on of the main
switch t
This time delay should be matched by adjusting the
time constant of the RC network which is calculated as:
3.3.1.3
After MOSFET is turned off, there will be some
oscillation on V
on ZC pin. To avoid that the MOSFET is turned on
mistriggerred
suppression timer is implemented. The time is
dependent on the voltage v
lower than the threshold V
applies, while a shorter time is set when the voltage v
is higher than the threshold.
3.3.1.4
After the gate drive goes to low, it can not be changed to high
during ring suppression time.
After ring suppression time, the gate drive can be turned on
when the ZC counter value is higher or equal to up/down
counter value.
However, it is also possible that the oscillation between
primary inductor and drain-source capacitor damps very fast
and IC can not detect enough zero crossings and ZC counter
value will not be high enough to turn on the gate drive. In this
case, a maximum off time is implemented. After gate drive
has been remained off for the period of T
will be turned on again regardless of the counter values and
V
frequency from going lower than 20kHz, otherwise which
will cause audible noise, during start up.
3.3.2
In the converter system, the primary current is sensed
by an external shunt resistor, which is connected
between low-side terminal of the main power switch
and the common ground. The sensed voltage across
the shunt resistor v
measurement unit, and its output voltage V
compared with the regulation voltage V
voltage V
is reset. As a result, the main power switch is switched
off. The relationship between the V
described by:
Version 2.3
V
ZC
td
t
1
. This function can effectively prevent the switching
=
=
=
T
------------ t
delay
3.3 V
C
osc
4
zc
1
exceeds the voltage V
, theoretically:
Ringing suppression time
Switch on determination
Switch Off Determination
–
-------------------------------- -
R zc1
R
cs
delay
DS
zc1
by
+
, which will also appear on the voltage
0.7
+
CS
R
R zc2
such
zc2
is applied to an internal current
ZC
ZCRS
oscillations,
. When the voltage v
, a longer preset time
FB
, the output flip-flop
OffMax
1
and the v
FB
, the gate drive
. Once the
a
ringing
CS
1
ZC
[2]
[3]
[4]
ZC
is
is
is
9
To avoid mistriggering caused by the voltage spike
across the shunt resistor at the turn on of the main
power switch, a leading edge blanking time, t
applied to the output of the comparator. In other words,
once the gate drive is turned on, the minimum on time
of the gate drive is the leading edge blanking time.
In addition, there is a maximum on time, t
limitation implemented in the IC. Once the gate drive
has been in high state longer than the maximum on
time, it will be turned off to prevent the switching
frequency from going too low because of long on time.
3.4
There is a cycle by cycle current limitation realized by the
current limit comparator to provide an overcurrent detection.
The source current of the MOSFET is sensed via a sense
resistor R
transformed to a sense voltage V
CS. If the voltage V
adjusted according to the Mains voltage, the comparator
immediately turns off the gate drive.
To prevent the Current Limitation process from distortions
caused by leading edge spikes, a Leading Edge Blanking
time (t
A further comparator is implemented to detect dangerous
current levels (V
transformer windings are shorted or if the secondary diode is
shorted. To avoid an accidental latch off, a spike blanking
time of t
comparator .
3.4.1
When the main bus voltage increases, the switch on time
becomes shorter and therefore the operating frequency is
also increased. As a result, for a constant primary current
limit, the maximum possible output power is increased,
which the converter may have not been designed to support.
To avoid such a situation, the internal foldback point
correction circuit varies the V
the bus voltage. This means the V
the bus voltage increases. To keep a constant maximum
input power of the converter, the required maximum V
LEB
) is integrated in the current sensing path.
CSSW
CS
. By means of R
Current Limitation
Foldback Point Correction
is integrated in the output path of the
CSSW
CS
) which could occur if one or more
exceeds an internal voltage limit,
Functional Description
CS
CS
CS
voltage limit according to
CS
which is fed into the pin
the source current is
will be decreased when
CoolSET
ICE2QR0665
April 27, 2010
®
LEB
- Q1
OnMax
, is
CS
,