NCP1901DR2G ONSEMI [ON Semiconductor], NCP1901DR2G Datasheet - Page 10

• Manufacturer Part Number: NCP1901DR2G
• Description: Primary Side Combination Resonant and PFC Controllers
• Manufacturer: ONSEMI [ON Semiconductor]

Off Time Control
voltage and it is adjusted every cycle to allow the inductor
current to reach zero before the next switch cycle begins.
The inductor is demagnetized once its current reaches zero.
Once the inductor is demagnetized the drain voltage of the
PFC switch begins to drop. The inductor demagnetization
is detected by sensing the voltage across the inductor using
an auxiliary winding. This winding is commonly known as
a zero crossing detector (ZCD) winding. This winding
provides a scaled version of the inductor voltage. Figure 6
shows the ZCD winding arrangement.
the PFC switch is on. The PZCD voltage is positive while
the PFC switch is off and current is flowing through the
inductor. The PZCD voltage drops to and rings around zero
volts once the inductor is demagnetized. Once a negative
transition is detected in the PZCD pin the next switch cycle
commences. A positive transition (corresponding to the
PFC switch turn off) arms the ZCD detector to prevent false
triggering. The arming of the ZCD detector is typically
2.1 V (V
1.5 V (V
diode. A resistor in series with the ZCD pin is required to
limit the current into the PZCD pin. The zener diode
prevents the voltage from exceeding the 10 V clamp or
going below ground. Figure 7 shows typical ZCD
waveforms.
PFC switch. A watchdog timer enables the PFC controller
if no switch pulses are detected for a period of 180 ms
(typical). The watchdog is also useful while operating at
light load because the amplitude of the ZCD signal may be
very small to cross the ZCD thresholds. The watchdog
PFC Switch
Voltage of
The PFC off time varies with the instantaneous line
A negative voltage appears on the ZCD winding while
The PZCD pin is internally clamped to 10 V with a zener
During startup there are no ZCD transitions to enable the
V
PDRV
Drain
PZCD
Figure 6. ZCD Winding Implementation
PZCD
PZCD
Figure 7. ZCD Winding Waveforms
decreasing).
increasing) and the triggering is typically
V
V
10 V
0 V
ZCD(high)
ZCD(low)
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10
timer is reset at the beginning of a PFC drive pulse and in
a PFC undervoltage fault.
PFC Compensation
output voltage, V
signal to an internal 2.5 V reference. As shown in Figure 28
a resistor divider from the PFC output voltage consisting of
R1 and R2 generates the PFC feedback signal.
input. The internal 2.5 V reference, V
amplifier non−inverting input. The reference is trimmed
during manufacturing to achieve an accuracy of ±3.2%.
Figure 5 shows the PFC error amplifier and sensing
network. Equation 5 is used to calculate the values of the
PFC feedback network.
gain, gm. That is, the output current is controlled by the
differential input voltage. The NCP1901 amplifier has a
typical gm of 95 mS. The PControl pin provides access to the
amplifier output for compensation. The compensation
network is ground referenced allowing the PFC feedback
signal to be used to detect an overvoltage condition.
selected to filter the bulk voltage ripple such that a constant
control voltage is maintained across the ac line cycle. A
capacitor between the PControl pin and ground sets a pole.
A pole at or below 20 Hz is enough to filter the ripple
voltage for a 50 and 60 Hz system. The low frequency pole,
f
where, C
ground.
is that the input is allowed to move independently with
respect to the output, since the compensation capacitor is
connected to ground. This allows dual usage of the
feedback pin by the error amplifier and by the overvoltage
comparator.
p
, of the system is calculated using Equation 6.
A transconductance error amplifier regulates the PFC
The feedback signal is applied to the amplifier inverting
A transconductance amplifier has a voltage−to−current
The compensation network on the PControl pin is
A key feature to using a transconductance type amplifier,
PControl
R2
R1
V
V
PFC
PFC
+ V
PFB
is the capacitor on the PControl pin to
PFC
PREF
f
p
, by comparing the PFC feedback
+
Figure 8.
@
2pC
I
R
PFB
1
R
) R
gm
PControl
2
−
+
2
) I
−
+
V
PFC Error
Amplifier
PREF
PREF
PFB
, is applied to the
@ R
1
(eq. 5)
(eq. 6)