NCP1901DR2G ONSEMI [ON Semiconductor], NCP1901DR2G Datasheet - Page 9

• Manufacturer Part Number: NCP1901DR2G
• Description: Primary Side Combination Resonant and PFC Controllers
• Manufacturer: ONSEMI [ON Semiconductor]

Voltage Reference
the controller to ease compensation requirements. The
reference voltage is typically 7.0 V. A 0.1 mF is required for
stability. The reference should not be loaded with external
circuitry.
PFC Regulator
(CrM). In CrM, the PFC inductor current, I
at the end of the switch cycle as shown in Figure 4. As seen
in Figure 4, the average input current, I
the ac line voltage, V
constant on time (t
(V
relationship between on time and system operating
conditions.
where, P
inductance and h is the system efficiency.
On Time Control
external timing capacitor on the PCT pin, C
constant current source, I
compared to the control voltage, V
voltage is constant for a given RMS line voltage and output
load, satisfying Equation 2. A voltage offset, V
is added to the C
range. The block diagram of the constant on time section
is shown in Figure 5.
The internal voltage reference, V
The PFC stage operates in critical conduction mode
High power factor is achieved in CrM by maintaining a
The NCP1901 controls the on time by charging an
ac(RMS)
out
) and load conditions. Equation 2 shows the
Figure 4. Inductor Current in CrM
is the output power, L is the PFC inductor
T
ramp to account for the control voltage
t
on
on
in(t)
) for a given RMS input voltage
+
.
h @ V
2 @ P
PCT(C)
ac(RMS)
out
. The C
@ L
REF
PControl
2
in(t)
, is brought out of
L(t)
, is in phase with
T
. The control
ramp is then
, reaches zero
PCT(offset)
T
, with a
http://onsemi.com
(eq. 2)
,
9
2.25 V and 5.65 V. An offset voltage greater than the
minimum PControl clamp voltage is added to the C
prior to comparing it to the control voltage signal. This
allows the PFC stage to stop the drive pulses (0% duty ratio)
and regulate at light loads. The delta between the Pcontrol
voltage needed to generate a PDRV pulse and the minimum
PControl Clamp voltage is V
C
drive pulse terminates once the C
voltage threshold, V
inductor current reaches zero detected by a transition on the
ZCD pin or the maximum off has been reached.
voltage is reached at low line and full load. In this operating
mode V
calculate the on time for a given C
Substituting t
rearranging Equation 4 provides a maximum value for C
where, V
3.0 V.
PControl
T
Figure 5. Constant On Time Control Block Diagram
The PControl voltage is internally clamped between
The timing capacitor is discharged and held low once the
The timing capacitor is sized such that the C
PZCD
ramp voltage plus offset reaches V
PCS
PFB
PCT
PControl
PCT(MAX)
V
DD
C
I
on
PFB
T
LEB
I
PCT(C)
t
is at its maximum. Equation 3 is used to
on(MAX)
w
> 5.65 V
< 2.25 V
in Equation 2 with Equation 3 and
, is the maximum PCT voltage, typically
Clamp
Clamp
h @ V
V
PCT(peak)
+
−
DD
V
2 @ P
PUVP
+
−
PFC UVP
Comparator
+
ac(RMS)
V
Shifter
−
+
Amplifier
−
+
V
+
−
PCS(ILIM)
Level
C
out
PREF
T
PCT(offset)
. A new cycle starts once the
Error
PFC
−
+
Comparator
@ V
@ L @ I
I
2
PCT(C)
PCS
T
@ V
V
PCT(MAX)
CC
V
voltage reaches its peak
T
+
POVP
.
PCT(C)
−
+
PCT(MAX)
Good
Comparator
Comparator
.
+
−
On time
V
PFC OVP
+
−
PControl
Comparator
ZCD
ZCD
+
−
PFCoff
T
S
R
Dominant
Reset
Latch
. The PFC
ramp peak
T
(eq. 3)
(eq. 4)
ramp
Q
Q
T
.