TLE5011_11 INFINEON [Infineon Technologies AG], TLE5011_11 Datasheet - Page 22

• Manufacturer Part Number: TLE5011_11
• Description: GMR Angle Sensor
• Manufacturer: INFINEON [Infineon Technologies AG]

3.8
The clock signal input “CLK” must fulfill certain requirements described in this section:
•
•
•
Figure 9
Table 12
Parameter
1) Minimum duty-cycle factor: t
3.9
The 3-pin SSC interface has a bidirectional data line (open drain), a serial clock signal, and Chip Select.
The SSC interface is designed to communicate with a microcontroller with bi-directional SSC interface supporting
open drain. Other microcontrollers may require an external NPN transistor.
This allows communication with SPI-compatible devices.
Final Data Sheet
Input Frequency
CLK Duty Cycle
CLK rise time
CLK fall time
PLL Frequency
Digital Clock
Digital Clock Periode
The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse
The PLL is triggered at the positive edge of the clock. If more than 2 edges are missing, a chip reset is
width and must be spike filtered.
The duty-cycle factor should be 0.5 but can deviate from the values limited by t
generated automatically.
Maximum duty-cycle factor: t
Clock Supply (CLK Timing Definition)
CLK Timing Definition
CLK Timing Specification
Synchronous Serial Communication Interface (SSC)
1)
CLKh(f_min)
Symbol
f
CLK
t
t
f
f
t
CLKh(f_max)
CLK
CLKr
CLKf
PLL
DIG
DIG
DUTY
t
CLKh
/ t
/ t
CLK(f_min)
CLK(f_min)
Limit Values
min.
3.8
30
-
-
-
-
-
with t
with t
t
CLK
CLK(f_min)
CLKh(f_max)
t
CLKl
22
typ.
4.00
50
-
-
100
25
40
= 1 / f
= t
CLK(f_min)
CLK(f_min)
max.
4.2
70
20
20
-
-
-
- t
CLKl(min)
%
ns
ns
MHz
Unit
MHz
MHz
ns
CLKh(f_min)
t
V
V
H
L
Notes
from V
from V
f
( 25 / 4 ) * f
4 / (25 * f
and t
CLK
* 25
CLKl(f_min)
L
H
V2.0, 2011-03
Specification
to V
to V
CLK
TLE5011
CLK
H
L
)
.