PXF4333V11 INFINEON [Infineon Technologies AG], PXF4333V11 Datasheet - Page 191

• Manufacturer Part Number: PXF4333V11
• Description: ABM 3G ATM Buf fer Manager
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 7-4
47
7.2.8
Internal Table 1: LCI Table Transfer Registers LCI0, LCI1, LCI2
These registers are used to access the internal Local Connection Identifier (LCI) table
containing 16384 entries (one entry serves for upstream and downstream direction).
Table 7-4
LCI0, LCI1 and LCI2 are the transfer registers for one 48-bit LCI table entry. The LCI
value representing the table entry which needs to be read or written must be written to
the Word Address Register (WAR). The dedicated LCI table entry is read into the LCI0/
LCI1/LCI2 Registers or modified by the LCI0/LCI1/LCI2 Register values with a write
mechanism. The associated Mask Registers MASK0 to MASK2 allow a bit-wise masking
for Write operation (0 - unmasked, 1 - masked). In case of Read operation, the dedicated
LCI0/LCI1/LCI2 register bit will be overwritten by the respective LCI table entry bit value.
In case of Write operation, the dedicated LCI0/LCI1/LCI2 register bit will modify the
respective LCI table entry bit value.
The Read or Write process is controlled by the Memory Address Register (MAR). The 5
LSBs (= Bit 4..0) of the MAR select the memory/table that will be accessed; to select the
LCI table bit field MAR(4:0) must be set to 0. Bit 5 of the MAR starts the transfer and is
automatically cleared after execution.
Table 7-5
Bit
Bit
LCISel(13:0)
Data Sheet
15
15
MASK2
LCI2
15
Unused(2:0)
7
shows an overview of the registers involved.
LCI Table Transfer Registers
Registers for LCI Table Access
WAR Register Mapping for LCI Table Access
0
0
14
Selects an LCI entry within the range (0..16383).
6
15
15
LCI RAM entry
MASK1
LCI1
13
5
0
0
12
4
LCISel(7:0)
0
15
15
191
MASK0
LCI0
11
LCISel(13:8)
3
0
0
10
2
Register Description
15
15
WAR (0..16383
PXF 4333 V1.1
RAM select:
9
1
LCI select:
MAR=00
2001-12-17
ABM-3G
H
8
0
D
)
0
0