LPC2364FB100 PHILIPS [NXP Semiconductors], LPC2364FB100 Datasheet - Page 19

• Manufacturer Part Number: LPC2364FB100
• Description: Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
LPC2364_66_68_1
Preliminary data sheet
7.10.1 USB device controller
7.10.2 Features
7.10 USB interface
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and a number (127 maximum) of peripherals. The host controller allocates the USB
bandwidth to attached devices through a token based protocol. The bus supports hot
plugging, unplugging and dynamic configuration of the devices. All transactions are
initiated by the host controller.
The device controller enables 12 Mbit/s data exchange with a USB host controller. It
consists of register interface, serial interface engine, endpoint buffer memory, and the
DMA controller. The serial interface engine decodes the USB data stream and writes data
to the appropriate end point buffer memory. The status of a completed USB transfer or
error condition is indicated via status registers. An interrupt is also generated if enabled.
The DMA controller when enabled transfers data between the endpoint buffer and the
USB RAM.
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Enhanced Ethernet features:
– Receive filtering.
– Multicast and broadcast frame support for both transmit and receive.
– Optional automatic FCS insertion (CRC) for transmit.
– Selectable automatic transmit frame padding.
– Over-length frame support for both transmit and receive allows any length frames.
– Promiscuous receive mode.
– Automatic collision back-off and frame retransmission.
– Includes power management by clock switching.
– Wake-on-LAN power management support allows system wake-up: using the
Physical interface:
– Attachment of external PHY chip through standard Reduced MII (RMII) interface.
– PHY register access is available via the Media Independent Interface Management
Fully compliant with USB 2.0 specification (full speed).
Supports 32 physical (16 logical) endpoints with a 4 kB USB buffer.
Supports Control, Bulk, Interrupt and Isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
Supports SoftConnect and GoodLink features.
While USB is in the Suspend mode, LPC2364/66/68 can enter one of the reduced
power down modes and wake up on a USB activity.
Supports DMA transfers with the DMA RAM of 8 kB on all non-control endpoints.
receive filters or a magic frame detection filter.
(MIIM) interface.
Rev. 01 — 22 September 2006
LPC2364/2366/2368
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Fast communication chip
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