LPC2364FB100 PHILIPS [NXP Semiconductors], LPC2364FB100 Datasheet - Page 2

• Manufacturer Part Number: LPC2364FB100
• Description: Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
LPC2364_66_68_1
Preliminary data sheet
Other Peripherals:
Standard ARM Test/Debug interface for compatibility with existing tools.
Emulation Trace Module supports real-time trace.
Single 3.3 V power supply (3.0 V to 3.6 V).
Four reduced power modes, Idle, Sleep, Power Down, and Deep Power down.
Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0
and PORT2 can be used as edge sensitive interrupt sources.
Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet
wake-up interrupt).
Two independent power domains allow fine tuning of power consumption based on
needed features.
Each peripheral has its own clock divider for further power saving.
Brownout detect with separate thresholds for interrupt and forced reset.
On-chip Power On Reset.
On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.
4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as
the system clock. When used as the CPU clock, does not allow CAN and USB to run.
Ethernet MAC with associated DMA controller. These functions reside on an
independent AHB bus.
USB 2.0 Full-Speed Device with on-chip PHY and associated DMA controller.
Four UARTs with fractional baud rate generation, one with modem control I/O, one
with IrDA support, all with FIFO.
CAN controller with two channels.
SPI controller.
Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate
for the SPI port, sharing its interrupt and pins. These can be used with the GPDMA
controller.
Three I
I
the GPDMA.
Secure Digital (SD) / MultiMediaCard (MMC) memory card interface (LPC2368
only).
70 General purpose I/O pins with configurable pull-up/down resistors.
10-bit ADC with input multiplexing among 6 pins.
10-bit DAC.
Four general purpose Timers/Counters with total of 8 capture inputs and 10
compare outputs. Each Timer block has an external count input.
One PWM / Timer block with support for three-phase motor control. The PWM has
two external count inputs.
Real Time Clock with separate power pin, clock source can be the RTC oscillator or
the APB clock.
2 kB SRAM powered from the RTC power pin, allowing data to be stored when the
rest of the chip is powered off.
Watchdog Timer. The watchdog timer can be clocked from the internal RC
oscillator, the RTC oscillator, or the APB clock.
2
S (Inter-IC Sound) interface for digital audio input or output. It can be used with
2
C-bus interfaces (one with open-drain and two with standard port pins).
Rev. 01 — 22 September 2006
LPC2364/2366/2368
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Fast communication chip
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