R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 177

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R5F61525

Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
7.2.3
DOFR is a 32-bit readable/writable register that specifies the offset to update the source and
destination addresses. Although different values are specified for individual channels, the same
values must be specified for the source and destination sides of a single channel.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
DMA Offset Register (DOFR)
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
Rev. 3.00 Mar. 14, 2006 Page 139 of 804
Section 7 DMA Controller (DMAC)
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
REJ09B0104-0300
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
0

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