R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 617
R5F61525
Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5F61525.pdf
(846 pages)
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Table 17.3 Registers/Parameters and Target Modes
Notes: 1. The setting is required when programming or erasing the user MAT in user boot mode.
17.7.1
The programming/erasing interface registers are 8-bit registers that can be accessed only in bytes.
These registers are initialized by a power-on reset.
(1)
FCCS monitors errors during programming/erasing the flash memory and requests the on-chip
program to be downloaded to the on-chip RAM.
Register/Parameter
Programming/
erasing interface
registers
Programming/
erasing interface
parameters
RAM emulation
Bit
Bit Name
Initial Value
R/W
Flash Code Control/Status Register (FCCS)
2. The setting may be required according to the combination of initiation mode and read
Programming/Erasing Interface Registers
target memory MAT.
—
R
7
1
FCCS
FPCS
FECS
FKEY
FMATS
FTDAR
DPFR
FPFR
FPEFEQ
FMPAR
FMPDR
FEBS
RAMER
—
R
6
0
Down-
load
O
O
O
O
O
O
—
R
5
0
Initiali-
zation
O
O
FLER
R
4
0
Section 17 Flash Memory (0.18-(m F-ZTAT Version)
Program-
ming
O
O*
O
O
O
1
—
R
3
0
Rev. 3.00 Mar. 14, 2006 Page 579 of 804
Erasure
O
O*
O
O
1
—
R
2
0
Read
O*
—
2
R
1
0
REJ09B0104-0300
RAM
Emulation
O
(R)/W
SCO
0
0
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