R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 349
R5F61525
Manufacturer Part Number
R5F61525
Description
32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5F61525.pdf
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9.4.4
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of
TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 9.32 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid
Table 9.32 Cascaded Combinations
(1)
Figure 9.18 shows an example of the setting procedure for cascaded operation.
Combination
Channels 1 and 2
Channels 4 and 5
Example of Cascaded Operation Setting Procedure
and the counter operates independently in phase counting mode.
Cascaded Operation
Figure 9.18 Example of Cascaded Operation Setting Procedure
<Cascaded operation>
Cascaded operation
Set cascading
Start count
Upper 16 Bits
TCNT_1
TCNT_4
[1]
[2]
[1]
[2]
Set bits TPSC2 to TPSC0 in the channel 1
(channel 4) TCR to B'1111 to select TCNT_2
(TCNT_5) overflow/underflow counting.
Set the CST bit in TSTR for the upper and lower
channels to 1 to start the count operation.
Lower 16 Bits
TCNT_2
TCNT_5
Rev. 3.00 Mar. 14, 2006 Page 311 of 804
Section 9 16-Bit Timer Pulse Unit (TPU)
REJ09B0104-0300
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