R5F61525 RENESAS [Renesas Technology Corp], R5F61525 Datasheet - Page 574

• Manufacturer Part Number: R5F61525
• Description: 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 14 Synchronous Serial Communication Unit (SSU)
(4)
Figure 14.9 shows a flowchart example of simultaneous transmission/reception. The data
transmission/reception is performed combining the data transmission and data reception as
mentioned above. The data transmission/reception is started by writing transmit data to SSTDR
with TE = RE = 1.
Before switching transmission mode (TE = 1) or reception mode (RE = 1) to
transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the
transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or
RE bit to 1.
Rev. 3.00 Mar. 14, 2006 Page 536 of 804
REJ09B0104-0300
[1]
[2]
[4]
[5]
[6]
No
Data Transmission/Reception
Read received data in SSRDR
Read receive data in SSRDR
RDRF automatically cleared
Overrun error processing
Clear ORER in SSSR
Dummy-read SSRDR
Consecutive data
Figure 14.8 Flowchart Example of Data Reception (SSU Mode)
End reception
End reception
Initial setting
Read SSSR
RDRF = 1?
ORER = 1?
reception?
RE = 0
Start
Yes
Yes
No
Yes
No
[3]
[1]
[2]
[3], [6] Receive error processing:
[4]
[5]
Note: Hatching boxes represent SSU internal operations.
Initial setting:
Specify the receive data format.
Start reception:
When SSRDR is dummy-read with RE = 1, reception is
started.
When a receive error occurs, execute the designated error
processing after reading the ORER bit in SSSR. After that,
clear the ORER bit to 0. While the ORER bit is set to 1,
transmission or reception is not resumed.
To continue single reception:
When continuing single reception, wait for time of t
while the RDRF flag is set to 1 and then read receive data
in SSRDR.
The next single reception starts after reading receive data
in SSRDR.
To complete reception:
To complete reception, read receive data after clearing the
RE bit to 0. When reading SSRDR without clearing the RE
bit, reception is resumed.
SUcyc