R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 107
R5S72611
Manufacturer Part Number
R5S72611
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72611.pdf
(1348 pages)
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3.5
3.5.1
The exception sources are as follows:
• FPU error (E): When FPSCR.DN = 0 and a denormalized number is input (No chance to occur
• Invalid operation (V): In case of an invalid operation, such as NaN input
• Division by zero (Z): Division with a zero divisor
• Overflow (O): When the operation result overflows
• Underflow (U): When the operation result underflows
• Inexact exception (I): When overflow, underflow, or rounding occurs
The FPU exception cause field in FPSCR contains bits corresponding to all of above sources E, V,
Z, O, U, and I, and the FPU exception flag and enable fields in FPSCR contain bits corresponding
to sources V, Z, O, U, and I, but not E. Thus, FPU errors cannot be disabled.
When an FPU exception occurs, the corresponding bit in the FPU exception cause field is set to 1,
and 1 is added to the corresponding bit in the FPU exception flag field. When an FPU exception
does not occur, the corresponding bit in the FPU exception cause field is cleared to 0, but the
corresponding bit in the FPU exception flag field remains unchanged.
3.5.2
FPU exception handling is initiated in the following cases:
• FPU error (E): FPSCR.DN = 0 and a denormalized number is input (No chance to occur in the
• Invalid operation (V): FPSCR.Enable.V = 1 and invalid operation
• Division by zero (Z): FPSCR.Enable.Z = 1 and division with a zero divisor
• Overflow (O): FPSCR.Enable.O = 1 and instruction with possibility of operation result
• Underflow (U): FPSCR.Enable.U = 1 and instruction with possibility of operation result
• Inexact exception (I): FPSCR.Enable.I = 1 and instruction with possibility of inexact operation
in the SH2A-FPU)
SH2A-FPU)
overflow
underflow
result
Floating-Point Exceptions
FPU Exception Sources
FPU Exception Handling
Rev. 2.00 Sep. 07, 2007 Page 75 of 1312
Section 3 Floating-Point Unit (FPU)
REJ09B0320-0200
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