R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 778

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 17 I
17.3.7
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
empty space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT
to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during
transferring data of ICDRS, continuous transfer is possible. ICDRT is initialized to H'FF.
ICDRT is initialized to H'FF by a power-on reset or deep standby mode.
17.3.8
ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR
transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a
receive-only register, therefore the CPU cannot write to this register.
ICDRR is initialized to H'FF by a power-on reset or deep standby mode.
17.3.9
ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from
ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from
ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the
CPU.
Rev. 2.00 Sep. 07, 2007 Page 746 of 1312
REJ09B0320-0200
I
I
I
2
2
2
2
C Bus Transmit Data Register (ICDRT)
C Bus Receive Data Register (ICDRR)
C Bus Shift Register (ICDRS)
C Bus Interface 3 (IIC3)
Initial value:
Initial value:
Initial value:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
R/W
—
—
R
7
1
7
1
7
R/W
—
—
R
6
1
6
1
6
R/W
—
—
R
5
1
5
1
5
R/W
—
—
R
4
1
4
1
4
R/W
—
—
R
3
1
3
1
3
R/W
—
—
R
2
1
2
1
2
R/W
—
—
R
1
1
1
1
1
R/W
—
—
R
0
1
0
1
0