R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 14

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.5
9.6
Section 10 Bus Monitor..................................................................................... 291
10.1 Register Descriptions......................................................................................................... 291
10.2 Bus Monitor Function........................................................................................................ 299
10.3 Usage Note......................................................................................................................... 304
Rev. 2.00 Sep. 07, 2007 Page xiv of xxxii
9.4.4
9.4.5
9.4.6
9.4.7
9.4.8
9.4.9
9.4.10 SDRAM Initialization Register 1 (SDIR1)........................................................... 231
9.4.11 SDRAM Power-Down Control Register (SDPWDCNT) ..................................... 232
9.4.12 SDRAM Deep-Power-Down Control Register (SDDPWDCNT) ........................ 233
9.4.13 SDRAMm Address Register (SDmADR) (m = 0, 1)............................................ 234
9.4.14 SDRAMm Timing Register (SDmTR) (m = 0, 1) ................................................ 235
9.4.15 SDRAMm Mode Register (SDmMOD) (m = 0, 1)............................................... 237
9.4.16 SDRAM Status Register (SDSTR) ....................................................................... 238
9.4.17 SDRAM Clock Stop Control Signal Setting Register (SDCKSCNT) .................. 240
9.4.18 AC Characteristics Switching Register (ACSWR) ............................................... 241
Operation ........................................................................................................................... 242
9.5.1
9.5.2
Usage Note......................................................................................................................... 288
9.6.1
9.6.2
9.6.3
10.1.1 Bus Monitor Enable Register (SYCBEEN) .......................................................... 292
10.1.2 Bus Monitor Status Register 1 (SYCBESTS1)..................................................... 293
10.1.3 Bus Monitor Status Register 2 (SYCBESTS2)..................................................... 295
10.1.4 Bus Error Control Register (SYCBESW)............................................................. 298
10.2.1 Operation when a Bus Error is Detected............................................................... 299
10.2.2 Illegal Address Access Detection Function .......................................................... 300
10.2.3 Bus Timeout Detection Function .......................................................................... 302
10.2.4 Combinations of Masters and Bus Errors ............................................................. 303
10.3.1 Operation when the CPU is Not Notified of a Bus Error...................................... 304
CSn Mode Register (CSMODn) (n = 0 to 6) ........................................................ 218
CSn Wait Control Register 1 (CS1WCNTn) (n = 0 to 6) ..................................... 221
CSn Wait Control Register 2 (CS2WCNTn) (n = 0 to 6) ..................................... 223
SDRAM Refresh Control Register 0 (SDRFCNT0)............................................. 226
SDRAM Refresh Control Register 1 (SDRFCNT1)............................................. 227
SDRAM Initialization Register 0 (SDIR0)........................................................... 229
CSC Interface........................................................................................................ 242
SDRAM Interface ................................................................................................. 252
Note on Power-on Reset Exception Handling and Deep Standby Mode
Cancellation .......................................................................................................... 288
Write Buffer.......................................................................................................... 288
Note on Transition to Software Standby Mode or Deep Standby Mode............... 289