R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 535

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(g)
In complementary PWM mode, the PWM pulse cycle is set in two registers—TGRA_3, in which
the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set.
The settings should be made so as to achieve the following relationship between these two
registers:
The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and
TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and
TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode
register (TMDR).
The updated PWM cycle is reflected from the next cycle when the data update is performed at the
crest, and from the current cycle when performed in the trough. Figure 12.42 illustrates the
operation when the PWM cycle is updated at the crest.
See the following section, Register Data Updating, for the method of updating the data in each
buffer register.
PWM Cycle Setting
TGRA_3
With dead time: TGRA_3 set value = TCDR set value + TDDR set value
Without dead time: TGRA_3 set value = TCDR set value + 1
Counter value TGRC_3
update
Figure 12.42 Example of PWM Cycle Updating
TGRA_3
update
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT_3
Rev. 2.00 Sep. 07, 2007 Page 503 of 1312
TCNT_4
REJ09B0320-0200
Time