R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 959

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

20.3.22 IEBus Receive Data Buffer 001 to 128 (IERB001 to IERB128)
IERB001 to IERB128 are 128-byte (8 × 128) buffers to which data to be transmitted during slave
transmission is written.
IERB001 to IERB128 are initialized by a power-on reset or in deep standby. The initial values are
undefined.
Note:
Bit
7 to 0
*
Bit Name
RBn
Reading these bits during slave reception (SRE in IEFLG is 1 and RXBSY in IERSR is
0) is prohibited. (Read value is undefined.)
Initial value:
Initial
Value
Undefined R*
[Legend]
n = 0011 to 128
R/W:
Bit:
—
7
R*
R/W
—
6
R*
Description
IEBus Receive Data Buffer
Data in RB001 to RB128 can be read when the RXBSY
bit in IERSR is set to 1. Data read from RB001 to
RB128 is the field data during slave receive.
Receive data is written starting with RB001 for the start
1-byte data, followed by RB002 and RB003 and so on,
and RB128 stores the last data.
Section 20 IEBus
—
5
R*
—
4
R*
RBn
—
3
R*
Rev. 2.00 Sep. 07, 2007 Page 927 of 1312
TM
—
2
R*
Controller (IEB) [R5S72612] [R5S72613]
—
1
R*
—
R*
0
REJ09B0320-0200