A3P060-1VQ144T ACTEL [Actel Corporation], A3P060-1VQ144T Datasheet - Page 10

• Manufacturer Part Number: A3P060-1VQ144T
• Description: Automotive ProASIC3 Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Automotive ProASIC3 Device Family Overview
1 -6
SRAM
Automotive ProASIC3 devices have embedded SRAM blocks along their north and south sides. Each
variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18,
512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that
can be configured with different bit widths on each port. For example, data can be sent through a
4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the
device JTAG port (ROM emulation mode) using the UJTAG macro.
PLL and CCC
Automotive ProASIC3 devices provide designers with very flexible clock conditioning circuit (CCC)
capabilities. Each member of the Automotive ProASIC3 family contains six CCCs. One CCC (center
west side) has a PLL.
The six CCC blocks are located at the four corners and the centers of the east and west sides. One
CCC (center west side) has a PLL.
All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay
operations as well as clock spine access.
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
Additional CCC specifications:
Global Clocking
Automotive ProASIC3 devices have extensive support for multiple clocking domains. In addition to
the CCC and PLL support described above, there is a comprehensive global clock distribution
network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three
quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the
core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for
rapid distribution of high-fanout nets.
I/Os with Advanced I/O Standards
The Automotive ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of
voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). Automotive ProASIC3 FPGAs support many different I/O
standards—single-ended and differential.
The I/Os are organized into banks, with two or four banks per device. The configuration of these
banks determines the I/O standards supported.
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Wide input frequency range (f
Output frequency range (f
Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns
2 programmable delay types for clock skew minimization
Clock frequency synthesis (for PLL only)
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output
divider configuration (for PLL only).
Output duty cycle = 50% ± 1.5% or better (for PLL only)
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single
global network used (for PLL only)
Maximum acquisition time is 300 µs (for PLL only)
Low power consumption of 5 mW
Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns (for PLL
only)
Four precise phases; maximum misalignment between adjacent phases of 40 ps × 350 MHz /
f
OUT_CCC
(for PLL only)
OUT_CCC
IN_CCC
) = 0.75 MHz to 350 MHz
v1.0
) = 1.5 MHz to 350 MHz