A3P060-1VQ144T ACTEL [Actel Corporation], A3P060-1VQ144T Datasheet - Page 23

• Manufacturer Part Number: A3P060-1VQ144T
• Description: Automotive ProASIC3 Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

1.
The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated
by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include
each output clock in the formula by adding its corresponding contribution (P
contribution.
I/O Output Buffer Contribution—P
N
α
β
F
RAM Contribution—P
N
F
β
F
β
page
PLL Contribution—P
F
F
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage.
If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency.
Below are some examples:
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled.
When nontristate output buffers are used, the enable rate should be 100%.
Table 2-12 • Toggle Rate Guidelines Recommended for Power Calculation
Component
α
α
CLK
READ-CLOCK
WRITE-CLOCK
CLKIN
CLKOUT
OUTPUTS
1
BLOCKS
2
3
2
1
2
is the I/O buffer enable rate—guidelines are provided in
is the RAM enable rate for read operations.
is the I/O buffer toggle rate—guidelines are provided in
P
P
P
•
•
is the RAM enable rate for write operations—guidelines are provided in
OUTPUTS
MEMORY
PLL
is the global clock signal frequency.
2-12.
is the input clock frequency.
The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at
half of the clock frequency.
The average toggle rate of an 8-bit counter is 25%:
–
–
–
–
–
–
= P
is the output clock frequency.
is the number of RAM blocks used in the design.
is the number of I/O output buffers used in the design.
Bit 0 (LSB) = 100%
Bit 1
Bit 2
…
Bit 7 (MSB) = 0.78125%
Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
AC13
= N
= P
is the memory read clock frequency.
is the memory write clock frequency.
AC11
OUTPUTS
+ P
AC14
* N
Toggle rate of VersaTile outputs
I/O buffer toggle rate
= 50%
= 25%
PLL
*
BLOCKS
* F
MEMORY
α
CLKOUT
2
/ 2 *
* F
READ-CLOCK
β
1
* P
1
OUTPUTS
AC10
v1.0
*
* F
β
Definition
CLK
2
+ P
Automotive ProASIC3 DC and Switching Characteristics
AC12
* N
BLOCK
Table
Table 2-13 on page
AC14
* F
2-12.
* F
WRITE-CLOCK
CLKOUT
product) to the total PLL
*
2-12.
β
3
Table 2-13 on
Guideline
10%
10%
2 - 11