A3P060-1VQ144T ACTEL [Actel Corporation], A3P060-1VQ144T Datasheet - Page 60

• Manufacturer Part Number: A3P060-1VQ144T
• Description: Automotive ProASIC3 Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Automotive ProASIC3 DC and Switching Characteristics
Table 2-79 • 3.3 V PCI/PCI-X
Table 2-80 • 3.3 V PCI/PCI-X
Table 2-81 • 3.3 V PCI/PCI-X
2 -4 8
Speed Grade
Std.
–1
Note:
Speed Grade
Std.
–1
Note:
Speed Grade
Std.
–1
Note:
For specific junction temperature and voltage supply levels, refer to
values.
For specific junction temperature and voltage supply levels, refer to
values.
For specific junction temperature and voltage supply levels, refer to
values.
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by Actel Designer software when
the user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no
support for bidirectional I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It
requires that one data bit be carried through two signal lines, so two pins are needed. It also
requires external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
on page
receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.
The values for the three driver resistors are different from those used in the LVPECL
implementation because the output standard specifications are different.
Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)
configuration (up to 40 nodes).
Automotive-Case Conditions: T
Applicable to Standard Plus I/O Banks
Automotive-Case Conditions: T
Applicable to Advanced I/O Banks
Automotive-Case Conditions: T
Applicable to Standard Plus I/O Banks
t
t
t
0.628
0.628
0.64
0.55
0.53
0.53
DOUT
DOUT
DOUT
2-49. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one
3.00
2.55
2.50
2.12
2.90
2.47
t
t
t
DP
DP
DP
0.05
0.04
0.04
0.04
0.05
0.05
t
t
t
DIN
DIN
DIN
0.93
0.79
0.92
0.78
0.90
0.77
t
t
t
J
J
J
PY
PY
PY
= 135°C, Worst-Case V
= 115°C, Worst-Case V
= 115°C, Worst-Case V
t
t
t
0.46
0.39
0.45
0.38
0.45
0.38
EOUT
EOUT
EOUT
v1.0
1.27
1.27
1.23
1.23
1.23
1.23
t
t
t
ZL
ZL
ZL
0.94
0.94
0.91
0.91
0.91
0.91
t
t
t
CC
CC
CC
ZH
ZH
ZH
= 1.425 V, Worst-Case V
= 1.425 V, Worst-Case V
= 1.425 V, Worst-Case V
3.12
2.65
3.02
2.57
3.02
2.57
t
t
t
Table 2-5 on page 2-5
Table 2-5 on page 2-5
Table 2-5 on page 2-5
LZ
LZ
LZ
3.60
3.06
3.48
2.96
3.48
2.96
t
t
t
HZ
HZ
HZ
2.49
2.49
2.40
2.41
2.40
2.41
t
t
t
ZLS
ZLS
ZLS
CCI
CCI
CCI
2.18
2.18
2.11
2.11
2.11
2.11
t
t
t
ZHS
ZHS
ZHS
= 3.0 V
= 3.0 V
= 3.0 V
for derating
for derating
for derating
Figure 2-12
Units
Units
Units
ns
ns
ns
ns
ns
ns