A3P060-1VQ144T ACTEL [Actel Corporation], A3P060-1VQ144T Datasheet - Page 69

• Manufacturer Part Number: A3P060-1VQ144T
• Description: Automotive ProASIC3 Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Table 2-93 • Input Data Register Propagation Delays
Figure 2-18 • Output Register Timing Diagram
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
Enable
CLK
Preset
Clear
DOUT
Data_out
ICLKQ
ISUD
IHD
ISUE
IHE
ICLR2Q
IPRE2Q
IREMCLR
IRECCLR
IREMPRE
IRECPRE
IWCLR
IWPRE
ICKMPWH
ICKMPWL
For specific junction temperature and voltage supply levels, refer to
values.
Output Register
Automotive-Case Conditions: T
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width HIGH for the Input Data Register
Clock Minimum Pulse Width LOW for the Input Data Register
50%
50%
t
1
OSUE
t
OHE
50%
50%
t
OSUD
0
t
t
OHD
OCLKQ
50%
J
50%
= 115°C, Worst-Case V
Description
50%
t
OWPRE
t
OPRE2Q
50%
50%
v1.0
t
t
ORECPRE
50%
OCLR2Q
50%
Automotive ProASIC3 DC and Switching Characteristics
t
OWCLR
50%
50%
CC
50%
= 1.425 V
t
ORECCLR
Table 2-5 on page 2-5
50%
t
OCKMPWH
t
50%
OREMPRE
0.29 0.34
0.31 0.37
0.00 0.00
0.44 0.52
0.00 0.00
0.54 0.64
0.54 0.64
0.00 0.00
0.27 0.31
0.00 0.00
0.27 0.31
0.25 0.30
0.25 0.30
0.41 0.48
0.37 0.43
t
50%
–1
OCKMPWL
for derating
Std. Units
t
OREMCLR
50%
50%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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