A3P060-1VQ144T ACTEL [Actel Corporation], A3P060-1VQ144T Datasheet - Page 9

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A3P060-1VQ144T

Manufacturer Part Number
A3P060-1VQ144T
Description
Automotive ProASIC3 Flash Family FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet
Figure 1-3 • VersaTile Configurations
X1
X2
X3
LUT-3 Equivalent
LUT-3
VersaTiles
The Automotive ProASIC3 core consists of VersaTiles, which have been enhanced beyond the
ProASIC
Refer to
User Nonvolatile FlashROM
Actel Automotive ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM.
The FlashROM can be used in diverse system applications:
The FlashROM is written using the standard Automotive ProASIC3 IEEE 1532 JTAG programming
interface.
The FlashROM can be programmed via the JTAG programming interface, and its contents can be
read back either through the JTAG programming interface or via direct FPGA core addressing. Note
that the FlashROM can only be programmed from the JTAG interface and cannot be programmed
from the internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-
byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8
banks and which of the 16 bytes within that bank are being read. The three most significant bits
(MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of
the FlashROM address define the byte.
The Actel Automotive ProASIC3 development software solutions, Libero
Environment (IDE) and Designer, have extensive support for the FlashROM. One such feature is
auto-generation of sequential programming files for applications requiring a unique serial number
in each part. Another feature allows the inclusion of static data for system version control. Data for
the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software
tools. Comprehensive programming file support is also included to allow for easy programming of
large numbers of parts with differing FlashROM contents.
Y
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Unique protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, infotainment systems)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management
PLUS®
Figure 1-3
core tiles. The Automotive ProASIC3 VersaTile supports the following:
for VersaTile configurations.
D-Flip-Flop with Clear or Set
Data
CLK
CLR
D-FF
v1.0
Y
Enable D-Flip-Flop with Clear or Set
Enable
Data
CLK
Automotive ProASIC3 Flash FPGAs
CLR
D-FF
®
Integrated Design
Y
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