TDA5204E1 Infineon Technologies, TDA5204E1 Datasheet - Page 17

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TDA5204E1

Manufacturer Part Number
TDA5204E1
Description
ASK Single Conversion Receiver 390MHz
Manufacturer
Infineon Technologies
Datasheet
Wireless Components
3.4.2
3.4.3
3.4.4
ing case and interference scenario to be expected during operation. The opti-
mum choice of AGC time constant and the threshold voltage is described in
Section 4.1.
Mixer
The Double Balanced Mixer downconverts the input frequency (RF) 390MHz to
the intermediate frequency (IF) at 10.7MHz with a voltage gain of approximately
21dB. A low pass filter with a corner frequency of 20MHz is built on chip in order
to suppress RF signals to appear at the IF output ( IFO pin). The IF output is
internally consisting of an emitter follower that has a source impedance of
approximately 330 Ω= to facilitate interfacing the pin directly to a standard
10.7MHz ceramic filter without additional matching circuitry.
PLL Synthesizer
The Phase Locked Loop synthesiser consists of a VCO, an asynchronous
divider chain, a phase detector with charge pump and a loop filter and is fully
implemented on-chip. The VCO is including spiral inductors and varactor
diodes. It’s nominal centre frequency is 800MHz. The FSEL pin (Pin 11) has to
be left open. No additional components are necessary. The oscillator signal is
fed both to the synthesiser divider chain and to the downconverting mixer. The
VCO signal is divided by two before it is fed to the mixer. The loop filter is also
realised fully on-chip.
Crystal Oscillator
The on-chip crystal oscillator circuitry allows for utilisation of quartzes both in
the 6 and 12MHz range as the overall division ratio of the PLL can be switched
between 64 and 128 via the CSEL (Pin 16 ) pin according to the following table.
The calculation of the value of the necessary quartz load capacitance is shown
in Section 4.3, the quartz frequency calculation is expained in Section 4.4.
Table 3-2 CSEL Pin Operating States
CSEL
Open
Shorted to ground
3 - 9
Crystal Frequency
Specification, December 2000
Functional Description
12.xx MHz
6.xx MHz
TDA 5204 E1
preliminary

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