PXB4220E Infineon Technologies AG, PXB4220E Datasheet - Page 111
PXB4220E
Manufacturer Part Number
PXB4220E
Description
Interworking Element for 8 E1/T1 Lines
Manufacturer
Infineon Technologies AG
Datasheet
1.PXB4220E.pdf
(290 pages)
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IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Interface Description
To allow the external SRTS generation logic to synchronize with the cell segmentation
process, the IWE8 will output a frame with type = 111 on the SDOR signal when the
segmentation of the first ATM cell for a selected channel starts. The first two sequences
of 8 ATM cells will contain a dummy RTS value which is programmable in the “ASIC
Configuration Register” (“acfg”, see
Chapter
7.2). From the third sequence on the
values received on the SDI input will be used.
The IWE8 has internal ‘RTS Buffers’ for 2 RTS values per port. When one of the ‘RTS
Buffers’ overflows, the value in excess will be omitted and a bit in the Extended Interrupt
Status Register 2 (eis2, see
Chapter
7.20) will be set. When ‘RTS Buffer’ underflow
occurs, the last received RTS value will be repeated in the next sequence of 8 ATM cells.
The RTS value extracted from a cycle of 8 ATM cells with sequence count 0 to 7, is
transmitted on SDOD when the cell with sequence count 1 from the next cycle is
received. The ‘RTS_valid’ field is used to indicate whether the extracted RTS value is
correct or not. An extracted RTS is accepted as valid if in the previous cycle of 8 cells
the cells with SN = 1, 3, 5 and 7 were present and were accepted as valid cells.
The buffer filling level is transmitted for use with the Adaptive Clock Method (ACM) and
is expressed as a number of octets contained in the ‘Reassembly Buffer’. The buffer
filling level is transmitted every time when a new ATM cell for the selected channel is
received.
Data Sheet
111
2003-01-20
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