PXB4221 Infineon Technologies AG, PXB4221 Datasheet - Page 95

• Manufacturer Part Number: PXB4221
• Description: IWE8 Interworking Element for 8 E1/T1 Lines
• Manufacturer: Infineon Technologies AG

FTFRS[0:7]
RFCLK
The receive system clock and transmit system clock are both 8.192 MHz, and may be
independent from each other. The datarate is 2048 Mbit/s. This means that each bit lasts
for 4 clock cycles.
Data on the system internal highway is structured in frames of 256 bits every 125 s . It
is transmitted in 32 slots numbered from 0 to 31 with slot 0 transmitted first. The data bits
of a slot are numbered from 1 to 8. The first transmitted bit ‘bit 1’ is the most significant
bit.
Figure 23
5.1.1.1
In T1 mode (Pin E1/T1 = 0) there is one F-channel carrying the F-bit (Frame Alignement
Signal/Data Link (FS/DL)) and 24 data channels numbered from 0 to 23. When using the
Data Sheet
Framer Receive Interface:
FRCLKn
FRDATn
FRMFBn
FRFRSn
Framer Transmit Interface:
FTCKOn
FTDATn
FTMFSn
FTFRSn
Figure 23
B8
B8
248
248
T1 Mode
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7
249
249
Framer Interface in FAM
shows the bit ordering.
250
250
251
251
Framer Transmit Frame Synchronization Pulse
FTFRS is generated at the beginning of timslot0 of every frame
Reference Clock
• Reference clock for the internal clock recovery circuit
• Depending on p_rx_em in pcfN: Optional emergency clock if
timeslot 31
timeslot 31
252
252
no transition on FRCLK is detected within 23 CLOCK cycles.
The segmentation continues using the RFCLK divided by four,
and using the byte-pattern programmed to a_emg_bpslct in
acfg for the cell payload.
253
253
254
254
255
255
256
256
1
1
2
2
95
3
3
timeslot 0
timeslot 0
4
4
PXB4219 / PXB4220 / PXB4221
5
5
6
6
7
7
8
8
9
9
Interface Description
10
10
11
11
timeslot 1
timeslot 1
12
12
13
13
2002-05-06
14
14
15
15
16
16