SAK-C164CM-4EF Infineon Technologies AG, SAK-C164CM-4EF Datasheet - Page 54

• Manufacturer Part Number: SAK-C164CM-4EF
• Description: 16-Bit Single-Chip Microcontrol ler
• Manufacturer: Infineon Technologies AG

Due to this adaptation to the input clock the frequency of
it is locked to
duration of individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and
For a period of
deviation D
where
So for a period of 3 TCLs @ 25 MHz (i.e.
and (3TCL)
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is neglectible.
Note: For all periods longer than 40 TCL the N = 40 value can be used (see
Figure 12
Data Sheet
Max. jitter
(
N
N
±26.5
× TCL)
±30
±20
±10
= number of consecutive TCLs and 1 ≤
±1
D
ns
N
N
min
:
1
Approximated Maximum Accumulated PLL Jitter
f
= 3TCL
min
OSC
This approximated formula is valid for
1
N
< –
=
. The slight variation causes a jitter of
× TCL the minimum value is computed using the corresponding
N
N
< –
NOM
× TCL
40 and 10 MHz
10
- 1.288 ns = 58.7 ns (@
NOM
- D
< –
Figure
N
f
CPU
; D
20
N
< –
N
50
25 MHz.
[ns] = ±(13.3 +
= 3): D
12).
N
3
≤ 40.
f
CPU
= (13.3 +
30
= 25 MHz).
f
CPU
N
f
CPU
× 6.3)/
3
is constantly adjusted so
× 6.3)/25 = 1.288 ns,
which also effects the
f
CPU
40
[MHz],
V1.0, 2001-05
Figure
C164CM
C164SM
MCD04455
10 MHz
16 MHz
20 MHz
25 MHz
12).
N