SAK-C167CS-4R33M Infineon Technologies AG, SAK-C167CS-4R33M Datasheet - Page 69
SAK-C167CS-4R33M
Manufacturer Part Number
SAK-C167CS-4R33M
Description
16-Bit Single-Chip Microcontroller
Manufacturer
Infineon Technologies AG
Datasheet
1.SAK-C167CS-4R33M.pdf
(80 pages)
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General Notes For The Following Timing Figures
These standard notes apply to all subsequent timing figures. Additional individual notes
are placed at the respective figure.
1)
2)
3)
4)
Figure 17
Data Sheet
CSxE, CSxL
A23-A0,
BHE
WRL, WRH,
WR, WrCS
D15-D0
Note: Write data is deactivated 1 TCL earlier
CLKOUT
Normal ALE
Extended ALE
The falling edge of signals RD and WR/WRH/WRL/WrCS is controlled by the Read/Write delay feature (bit
BUSCON.RWDCx).
The rising edge of signal WR/WRH/WRL/WrCS is controlled by the early write feature (bit BUSCON.EWENx).
A bus cycle is extended here, if MCTC waitstates are selected or if the READY input is sampled inactive.
A bus cycle is extended here, if an MTTC waitstate is selected.
if early write is enabled (same timing).
Demultiplexed Bus, Write Access
tc
tc
tc
16
19
19
tc
11
tc
tc
Extended ALE Cycle
16
11
tc
tc
19
19
Normal ALE Cycle
65
tc
tc
tc
12
11
11
1)
tc
Valid
21
tc
tc
12
10
MCTC
3)
tc
Data OUT
12
tc
2)
12
tc
MTTC
17
4)
tc
C167CS-4R
20
V2.0, 2000-06
C167CS-L
tc
18
MCT04435
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