SAF-C161S-L25M Infineon Technologies AG, SAF-C161S-L25M Datasheet - Page 52
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SAF-C161S-L25M
Manufacturer Part Number
SAF-C161S-L25M
Description
16-Bit Single-Chip Microcontroller
Manufacturer
Infineon Technologies AG
Datasheet
1.SAF-C161S-L25M.pdf
(75 pages)
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5.2
Table 14
Parameter
Oscillator
period
High time
Low time
Rise time
Fall time
1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock
2) The clock input signal must reach the defined levels
3) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (
Figure 12
Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is
Data Sheet
generation mode. Please see respective table above.
direct drive mode depends on the duty cycle of the clock input signal.
limited to a range of 4 MHz to 16 MHz.
It is strongly recommended to measure the oscillation allowance (or margin) in the
final target system (layout) to determine the optimum parameters for the oscillator
operation. Please refer to the limits specified by the crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is verified by design
only (not tested in production).
2)
2)
2)
2)
External Clock Drive XTAL1
0.5
External Clock Drive XTAL1 (Operating Conditions apply)
External Clock Drive XTAL1
V
DD
Symbol
t
t
t
t
t
OSC
1
2
3
4
SR 40
SR 20
SR 20
SR –
SR –
t
1
Min.
Direct Drive
3)
3)
1:1
Max.
–
–
–
8
8
48
t
V
2
IL2
Min.
20
5
5
–
–
and
Prescaler
V
t
t
OSC
3
IH2
2:1
.
Max.
–
–
–
5
5
Timing Characteristics
Min.
60
10
10
–
–
t
1)
4
MCT02534
PLL
1:N
V
V
IH2
IL
Max.
500
–
–
10
10
V1.0, 2003-11
1)
C161S
Unit
ns
ns
ns
ns
ns
f
CPU
) in