MCF5232 ETC, MCF5232 Datasheet - Page 5

• Manufacturer Part Number: MCF5232
• Description: Integrated Microprocessor Hardware Specification
• Manufacturer: ETC

1.3
The following section gives a brief overview of this family’s feature set. For more detailed information see
the MCF5235 Reference Manual (MCF5235RM).
1.3.1
Freescale Semiconductor
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Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data path on-chip
— Processor core runs at twice the bus frequency
— Sixteen general-purpose 32-bit data and address registers
— Implements the ColdFire Instruction Set Architecture, ISA_A+, with extensions to support the
— Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support 32-bit
— Illegal instruction decode that allows for 68K emulation support
Enhanced Time Processor Unit (eTPU)
— Event triggered VLIW processor timer subsystem
— 32 channels
— 24-bit timer resolution
— 6 Kbyte of code memory and 1.5 Kbyte of data memory
— Variable number of parameters allocatable per channel
— Double match/capture channels
— Angle mode support
— DMA and interrupt request support
— Nexus Class 1 Debug support
System debug support
— Integrated debug supports both ColdFire Debug and Nexus class 1 features on a single port
— Unified programming model including both ColdFire and Nexus debug registers
— Real time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging
— Real time debug support, with two user-visible hardware breakpoint registers (PC and address
On-chip memories
— 8-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache
— 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus
Features
Feature Overview
user stack pointer register, and 4 new instructions for improved bit processing
signal processing algorithms
with cross triggering operations for ease of use
with optional data) that can be configured into a 1- or 2-level trigger
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3
Preliminary
Overview
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