MCF5232 ETC, MCF5232 Datasheet - Page 50

• Manufacturer Part Number: MCF5232
• Description: Integrated Microprocessor Hardware Specification
• Manufacturer: ETC

Preliminary Electrical Characteristics
Figure 18
6.10 Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
6.10.1 MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and
The receiver functions correctly up to a ERXCLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
ERXCLK frequency.
Table 37
50
I2C_SCL
I2C_SDA
lists MII receive channel timings.
shows timing for the values in
ERXCLK)
NOTES:
1
2
3
Num
Note: Output numbers depend on the value programmed into the IFDR; an IFDR
programmed with the maximum frequency (IFDR = 0x20) results in minimum output
timings as shown in
transition time to move it to the middle of the I2C_SCL low period. The actual position is
affected by the prescale and division values programmed into the IFDR; however, the
numbers given in
Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can
only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on
external signal capacitance and pull-up resistor values.
Specified at a nominal 50-pF load.
I7
I8
I9
Table 36. I
1
1
1
I1
Data setup time
Start condition setup time (for repeated start
condition only)
Stop condition setup time
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3
2
C Output Timing Specifications between I2C_SCL and I2C_SDA
I2
Table 36
Table
I4
Characteristic
Figure 18. I
36. The I
are minimum values.
Table 35
2
C interface is designed to scale the actual data
I6
2
C Input/Output Timings
Preliminary
and
I7
Table
36.
Min
20
10
2
I8
Max
—
—
—
I5
I3
Units
Freescale Semiconductor
t
t
t
cyc
cyc
cyc
I9