M306V5EESP Mitsubishi, M306V5EESP Datasheet - Page 127
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M306V5EESP
Manufacturer Part Number
M306V5EESP
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Manufacturer
Mitsubishi
Datasheet
1.M306V5EESP.pdf
(262 pages)
- Current page: 127 of 262
- Download datasheet (2Mb)
Rev. 1.0
(5) I
The I
These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request
signal occurs immediately after the number of bits specified with these bits are transmitted.
When a START condition is received, these bits become “000
mitted and received in 8 bits.
Note: When the bit counter value = “111
This bit enables usage of the multimaster I
disable status is provided, so the SDA and the SCL become high-impedance. When the bit is set to
“1,” use of the interface is enabled.
When ESO = “0,” the following is performed.
• PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I
• Writing data to the I
This bit decides whether or not to recognize slave addresses. When this bit is set to “0,” the address-
ing format is selected, so that address data is recognized. When a match is found between a slave
address and address data as a result of comparison or when a general call (refer to “(6) I
register,” bit 1) is received, transmission processing can be performed. When this bit is set to “1,” the
free data format is selected, so that slave addresses are not recognized.
This bit selects a slave address specification format. When this bit is set to “0,” the 7-bit addressing
format is selected. In this case, only the high-order 7 bits (slave address) of the I
are compared with address data. When this bit is set to “1,” the 10-bit addressing format is selected, all
the bits of the I
Bits 0 to 2: bit counter (BC0–BC2)
Bit 3: I
Bit 4: data format selection bit (ALS)
Bit 5: addressing format selection bit (10BIT SAD)
2
Ci control register (i = 0, 1)
2
Ci control register controls the data communication format.
2
C-BUS interface i use enable bit (ESO)
2
Ci address register are compared with address data.
2
Ci data shift register and the I
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
2
,” a STOP condition and START condition cannot be waited.
2
C-BUS interface i. When this bit is set to “0,” the use
2
Ci transmit buffer register is disabled.
2
” and the address data is always trans-
2
Ci status register).
and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
M306V5ME-XXXSP
2
M306V5EESP
Ci address register
2
Ci status
127
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