M306V5EESP Mitsubishi, M306V5EESP Datasheet - Page 56
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M306V5EESP
Manufacturer Part Number
M306V5EESP
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Manufacturer
Mitsubishi
Datasheet
1.M306V5EESP.pdf
(262 pages)
- Current page: 56 of 262
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MITSUBISHI MICROCOMPUTERS
M306V5ME-XXXSP
M306V5EESP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2.8 Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is
a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog
timer interrupt is generated when an underflow occurs in the watchdog timer. Bit 7 of the watchdog timer
control register (address 000F
) selects the prescaler division ratio (by 16 or by 128). Thus the watchdog
16
timer’s period can be calculated as given below. The watchdog timer’s period is, however, subject to an
error due to the pre-scaler.
pre-scaler dividing ratio (16 or 128)
watchdog timer count (32768)
Watchdog timer period =
BCLK
For example suppose that BCLK runs at 10 MHz and that 16 has been chosen for the dividing ratio of the
pre-scaler, then the watchdog timer’s period becomes approximately 52.4 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E
) and when
16
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E
).
16
Figure 2.8.1 shows the block diagram of the watchdog timer. Figure 2.8.2 shows the watchdog timer control
register and Figure 2.8.3 shows the watchdog timer start register.
Rev. 1.0
56
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