M306V5EESP Mitsubishi, M306V5EESP Datasheet - Page 130

• Manufacturer Part Number: M306V5EESP
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
• Manufacturer: Mitsubishi

130
This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the
PIN bit changes from “1” to “0.” At the same time, an interrupt request signal is sent to the CPU. The
PIN bit is set to “0” in synchronization with a falling edge of the last clock (including the ACK clock) of
an internal clock and an interrupt request signal occurs in synchronization with a falling edge of the
PIN bit. When detecting the STOP condition in slave, the multi-master I
request bit (IR) is set to “1” (interrupt requested) regardless of falling of PIN bit. When the PIN bit is “0,”
the SCL is kept in the “0” state and clock generation is disabled. Figure 2.11.41 shows an interrupt
request signal generating timing chart.
The PIN bit is set to “1” in any one of the following conditions.
Note : It takes 8 BCLK cycles or more until PIN bit becomes “1” after write instructions are executed
The conditions in which the PIN bit is set to “0” are shown below:
This bit indicates the status of use of the bus system. When this bit is set to “0,” this bus system is not
busy and a START condition can be generated. When this bit is set to “1,” this bus system is busy and
the occurrence of a START condition is disabled by the START condition duplication prevention func-
tion (See note).
This flag can be written by software only in the master transmission mode. In the other modes, this bit is
set to “1” by detecting a START condition and set to “0” by detecting a STOP condition. When the ESO bit
of the I
This bit decides the direction of transfer for data communication. When this bit is “0,” the reception
mode is selected and the data of a transmitting device is received. When the bit is “1,” the transmission
mode is selected and address data and control data are output into the SDA in synchronization with
the clock generated on the SCL.
When the ALS bit of the I
is set to “1” (transmit) if the least significant bit (R/W bit) of the address data transmitted by the master
is “1.” When the ALS bit is “0” and the R/W bit is “0,” the TRX bit is cleared to “0” (receive).
The TRX bit is cleared to “0” in one of the following conditions.
Bit 4: I
Bit 5: bus busy flag (BB)
Bit 6: communication mode specification bit (transfer direction specification bit: TRX)
• Writing “1” to the PIN bit
• Executing a write instruction to the I
• When the ESO bit is “0”
• At reset
• Immediately after completion of 1-byte data transmission (including when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately after completion of slave address or
• In the slave reception mode, with ALS = “1” and immediately after completion of address data reception
• When arbitration lost is detected.
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START condition duplication prevention
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset
general call address reception
function (Note).
2
to these registers.
2
Ci control register is “0” and at reset, the BB flag is kept in the “0” state.
C-BUS interface i interrupt request bit (PIN)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
2
Ci control register is “0” in the slave reception mode is selected, the TRX bit
2
Ci data shift register or the I
___
___
and ON-SCREEN DISPLAY CONTROLLER
2
Ci transmit buffer register (See note).
MITSUBISHI MICROCOMPUTERS
M306V5ME-XXXSP
2
C-BUS interface interrupt
M306V5EESP
Rev. 1.0