K9F1208Q0A-XXB0 Samsung semiconductor, K9F1208Q0A-XXB0 Datasheet - Page 27
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K9F1208Q0A-XXB0
Manufacturer Part Number
K9F1208Q0A-XXB0
Description
512Mb/256Mb 1.8V NAND Flash Errata
Manufacturer
Samsung semiconductor
Datasheet
1.K9F1208Q0A-XXB0.pdf
(39 pages)
K9F5608U0C-VCB0,VIB0,FCB0,FIB0
K9F5608Q0C-DCB0,DIB0,HCB0,HIB0
K9F5608U0C-YCB0,YIB0,PCB0,PIB0
K9F5608U0C-DCB0,DIB0,HCB0,HIB0
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg-
ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Two types of operations are available : random read, serial page read.
The random read mode is enabled when the page address is changed. The 528 bytes(X8 device) or 264 words(X16 device) of data
within the selected page are transferred to the data registers in less than 10 s(t
of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out
in 50ns cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data starting from the selected col-
umn address up to the last column address[column 511/ 527(X8 device) 255 /263(X16 device) depending on the state of GND input
pin].
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of 512
~527 bytes(X8 device) or 256~263 words(X16 device) may be selectively accessed by writing the Read2 command with GND input
pin low. Addresses A
ignored in X8 device case or A
main area. Figures 8,9 show typical sequence and timings for each read operation.
Sequential Row Read is available only on K9F5608U0C_Y,P or K9F5608U0C_V,F :
After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 10 s
again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation
is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of
each page may be sequentially read. The Sequential Read 1 and 2 operation is allowed only within a block and after the last page
of a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the
next block, read command and address must be given. Figures 8-1, 9-1 show typical sequence and timings for sequential row read
operation.
NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
Figure8. Read1 Operation
CLE
CE
WE
ALE
R/B
RE
I/Ox
array (00h) at next cycle.
00h
X16 device : A
X8 device : A
0~
A
Start Add.(3Cycle)
3
(X8 device) or A
3~
0
A
0
~ A
~ A
7
must be "L" in X16 device case. The Read1 command is needed to move the pointer back to the
7
7
& A
& A
01h command is only available on X8 device(K9F5608X0C).
9
9
~ A
~ A
0~
A
24
24
2
(X16 device) set the starting address of the spare area while addresses A
K9F5616Q0C-DCB0,DIB0,HCB0,HIB0
K9F5616U0C-YCB0,YIB0,PCB0,PIB0
K9F5616U0C-DCB0,DIB0,HCB0,HIB0
t
R
(00h Command)
Data Field
Main array
On K9F5608U0C_Y,P or K9F5608U0C_V,F
CE must be held
low during tR
26
Spare Field
R
). The system controller can detect the completion
Data Output(Sequential)
1)
1st half array
FLASH MEMORY
(01h Command)
Data Field
2st half array
Spare Field
4
~A
7
are