GS88018AT-133 ETC, GS88018AT-133 Datasheet - Page 10
GS88018AT-133
Manufacturer Part Number
GS88018AT-133
Description
512K x 18/ 256K x 32/ 256K x 36 9Mb Sync Burst SRAMs
Manufacturer
ETC
Datasheet
1.GS88018AT-133.pdf
(26 pages)
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Notes:
1.
2.
3.
Rev: 1.02 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Simplified State Diagram with G
The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
X
X
CW
First Write
Burst Write
W
W
CW
10/26
W
CR
R
CR
R
Deselect
X
GS88018/32/36AT-250/225/200/166/150/133
CW
W
CW
W
R
CR
First Read
Burst Read
R
R
CR
X
X
© 2001, Giga Semiconductor, Inc.
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