GS88018AT-133 ETC, GS88018AT-133 Datasheet - Page 9
GS88018AT-133
Manufacturer Part Number
GS88018AT-133
Description
512K x 18/ 256K x 32/ 256K x 36 9Mb Sync Burst SRAMs
Manufacturer
ETC
Datasheet
1.GS88018AT-133.pdf
(26 pages)
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Notes:
1.
2.
3.
Rev: 1.02 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Simplified State Diagram
The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B
that ADSP is tied high and ADSC is tied low.
The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
X
CW
X
First Write
Burst Write
W
W
CW
9/26
W
CR
R
CR
R
Deselect
X
GS88018/32/36AT-250/225/200/166/150/133
R
CR
First Read
Burst Read
R
A
, B
B
R
, B
C
, B
CR
D
, BW, and GW) control inputs, and
X
X
© 2001, Giga Semiconductor, Inc.
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