GS88018AT-133 ETC, GS88018AT-133 Datasheet - Page 19
![no-image](/images/no-image-200.jpg)
GS88018AT-133
Manufacturer Part Number
GS88018AT-133
Description
512K x 18/ 256K x 32/ 256K x 36 9Mb Sync Burst SRAMs
Manufacturer
ETC
Datasheet
1.GS88018AT-133.pdf
(26 pages)
- Current page: 19 of 26
- Download datasheet (757Kb)
Rev: 1.02 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Flow Through Read-Write Cycle Timing
DQ
A
ADSC
B
ADSP
A
–
A
ADV
DQ
0
GW
BW
–
–
CK
B
A
E
E
E
G
D
D
n
1
2
3
Hi-Z
tS tH
tS
tS tH
tS
tS
RD1
tH
tH
tH
tKQ
Single Read
tOE
tS tH
tS tH
tS
Q1
tOHZ
A
E
2
tKH
and E
19/26
tS
tKL
tS
tS
tS tH
D1A
WR1
WR1
3
only sampled with ADSP and ADSC
tH
tH
tKC
Single Write
tH
ADSC initiated read
GS88018/32/36AT-250/225/200/166/150/133
RD2
ADSP is blocked by E inactive
Burst wrap around to it’s initial state
Q2
A
E
1
masks ADSP
Burst Read
Q2
B
© 2001, Giga Semiconductor, Inc.
Deselected with E
Q2c
Q2
D
Q2
3
A
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