UPD64084 NEC, UPD64084 Datasheet - Page 12

• Manufacturer Part Number: UPD64084
• Description: THREE-DIMENSIONAL Y/C SEPARATION LSI WITH ON-CHIP MEMORY
• Manufacturer: NEC

2.2
2.3
12
Remark
Table 2-2 lists filters used in each mode.
Note Setting serial bus register SA09h: D0 (VFLTH) enables through output.
The following diagram shows a model of system delays (video signal delays).
YCS mode
(NRMD = 0)
YCS+ mode
(NRMD = 1)
Vertical contour
compensation /
Y peaking
Filter Processing
System Delay
Mode
C Sync. Input
Composite
1 corresponds to a one-clock pulse delay (4f
Input
AYI
CSI
Standard / nonstandard / killer
Standard signal detected
Nonstandard signal detected
Killer signal detected
Standard or horizontal
nonstandard signal detected
Vertical nonstandard signal
detected
Killer signal detected
SA02h:D5
signal detection
ADC
10
-
EXADINS
1
0
1H Delay
Figure 2-1. System Delay Model
Timing
Gen.
910
Table 2-2. Filter Matrix
Data Sheet S16021EJ2V0DS
Frame comb
Still picture
Line comb + Frame recursive
portion
Effective-picture period
SC
CNR/Delay
YCS/YNR
or 910 f
21
21
Y output: Through (Y/C separation stop)
Y output: Through (Y/C separation stop)
Moving picture
H
Line comb
Line comb
C output: Separated C signal
C output: Separated C signal
portion
= about 69.8 ns).
Active
Filter selected
Delay
Filter
CDL
Line comb
0~ 7
SA03h:D2-D0
4
Line comb
Horizontal
(11 s)
Y-DAC
C-DAC
Blanking period
1
1
DYCO9-2
AYO
ACO
Band-pass
Band-pass
Band-pass
Band-pass
Y Outpur
C Output
(1H to 22H)
PD64084
Through
Vertical
Note
Note
Note
Note