UPD64084 NEC, UPD64084 Datasheet - Page 14

• Manufacturer Part Number: UPD64084
• Description: THREE-DIMENSIONAL Y/C SEPARATION LSI WITH ON-CHIP MEMORY
• Manufacturer: NEC

3. VIDEO SIGNAL INPUT BLOCK
3.1
internal 10-bit ADC (EXADINS = 0).
(EXADINS = 1).
3.2
difference between that level and the internal fixed value of 256 LSB levels, and outputs the feedback level.
to 256 LSB. Pull down the VCLY pin via a 0.1 F bypass capacitor and a 10 to 47 F electrolysis capacitor for loop
filter.
14
This block converts analog video signals to digital form.
The composite signal is input to the AYI pin. This analog video (composite) signal converts to digital video signal at
In case of external ADC used, 10-bit composite signals in digital form are input to the DYCO9 to DYCO0 pins
This circuit reproduces the pedestal level of a video signal. The pedestal level error detection circuit detects the
This output signal is connected to VCLY pin via internal resistor to feed back to video signal for fixing pedestal level
Caution In case of H-Sync input level is bigger than 256LSB, this pedestal level also becomes over 256LSB.
Composite input
(When the internal ADC used)
= 0.8 V
140 IRE
Video Signal Inputs
Pedestal Level Reproduction
Composite input
(When the external
ADC used)
p-p
Analog section supply voltage 2.5 V
Do not use this circuit when the external ADC is used.
47 k
15 k
Figure 3-1. Video Signal Input Block Diagram
V
V
V
V
IN
RT
CL
RB
PC659A
DB
10 to 47
1
Data Sheet S16021EJ2V0DS
-DB
PCL
CLK
0.1
0.1
0.1
0.1
0.1
8
F
F
F
F
F
F
100
100
4f
1
SC
,910f
F
8
2
H
DYCO9-2
DYCO1-0
VCOMY
AGND
AVDD
VRBY
VRTY
VCLY
ALTF
AYI
ST0
8
2
Sampling clock
Clamp
10-bit
( 10)
ADC
10
CLK
10
1
0
4f
Clamp level
EXADINS
Clamp pulse generator
feedback
SC
256
Pedestal level error
10
ST0S=01
detection
PD64084
Internal