GS815018AB GSI [GSI Technology], GS815018AB Datasheet - Page 4

• Manufacturer Part Number: GS815018AB
• Description: 1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM
• Manufacturer: GSI [GSI Technology]

Read Operations
Pipelined Read
A read cycle begins when the RAM captures logic 0 on SS and logic 1 on SW at the rising edge of K (and the falling edge of K).
Address inputs captured on that clock edge are propigated into the RAM, which delivers data to the input of the output registers.
The second rising edge of K fires the output registers and releases read data to the output drivers. If G is held active low, the
drivers drive the data onto the output pins. Read data is sustained on the output pins as long as G is held low or until the next rising
edge of K, at which point the outputs may update to new data or deselect, depending on what control command was registered at
the second rising edge of K.
Dual Cycle Deselect
Chip deselect (SS = logic 1) is pipelined to the same degree as read data. Therefore, a deselect command entered on the rising edge
of K is acted upon in response to the next rising edge of K.
Rev: 1.05 10/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS815018/36 BGA Pin Description
B
A
Symbol
, B
V
V
TMS
TDO
DQ
DQ
DQ
DQ
TCK
V
SW
TDI
V
B
NC
CK
CK
M1
M2
ZQ
SS
ZZ
DDQ
REF
G
A
, B
DD
SS
A
B
C
D
C
, B
D
Type
I/O
—
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Read Operation Protocol Select—Selects Register-Register read operations; must be tied high in this
Read Operation Protocol Select—Selects Register-Register read operations; must be tied low in this
Byte Write Enable for DQ
4/25
FLXDrive-II™ Output Impedance Control
Sleep mode control; active high
Clock Input Signal; active high
Clock Input Signal; active low
Data Input and Output pins
Output driver power supply
Output Enable; active low
Synchronous Select Input
Input Reference Voltage
Write Enable; active low
Scan Test Mode Select
I/O and Core Ground
Scan Test Data Out
Core power supply
Scan Test Data In
Scan Test Clock
Address Inputs
Description
No Connect
A
, DQ
device
device
B
, DQ
GS815018/36AB-357/333/300/250
C
, DQ
D
I/Os; active low
© 2003, GSI Technology
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